Broadcom and Marvell Are Taking Over the Underlying Narrative of AI Data Centers

Broadcom and Marvell are the two dominant players in the custom ASIC space.

Custom ASIC is one of the fastest-growing segments in semiconductors. The reason this matters, or the main point I want to make here, is that

Moore’s Law has gradually broken down after the 28nm process node, meaning that shrinking chip area no longer delivers higher transistor density, greater computing power, lower power consumption, or faster computing speed through higher 0/1 transition frequency.

At today’s 3 nm and 2 nm nodes, the design and tape-out cost for a single wafer exceeds $500 million, and the industry’s entire economic structure is bound to be reorganized.

How will it be reorganized?

If you are Google, and you spend more than $50 billion a year on electricity and depreciation costs related to TPU training and inference, then a custom chip that can cut inference token costs by 30% means substantial savings.

Over the past five years, an increasing share of Hyperscaler capital expenditures has gone into in-house chips, while the marginal dollar growth of off-the-shelf Nvidia GPUs has gradually flattened. Google TPU v7, AWS Trainium 2 and Trainium 3, Microsoft Maia 100 and Maia 200, Meta MTIA, and Apple’s in-house AI server chip officially confirmed in 2026.

Globally, there are really only two companies capable of taking on ASIC co-design work at hyperscaler scale: Broadcom and Marvell. According to Tom's Hardware’s industry research, these two companies together account for about 95% of the hyperscaler custom AI accelerator co-design market.

What 95% concentration means is this: over the next five to ten years, among all the AI capital expenditures hyperscalers deploy, the birth of every in-house XPU will almost always pass through the hands of one of these two companies.

The rise of custom ASIC is not a business story; it is an economic restructuring forced into existence after physics reached its limit

High customer concentration

First, custom ASIC customers are highly concentrated among top-tier hyperscalers.

In 1974, Dennard proposed a scaling law at IBM Research, finding that as chips shrink in size, performance can improve while power consumption is maintained.

But by the 90nm node, severe leakage issues imposed by physical constants prevented voltage from continuing to decline proportionally, causing power density to surge. This was the physical reason CPU clock speeds stopped rising around 2005, and the starting point for the later rise of multicore architectures.

Starting at 28nm, the cost per transistor no longer fell; instead, it began to rise, causing manufacturing and design costs to increase sharply.

Today, 3nm tape-out costs as much as $500 million, and 2nm is closer to $1 billion. Such extremely high fixed costs mean that only top-tier data center giants consuming millions of chips per year can amortize the cost through massive volume.

According to TSMC and industry roadmaps, process technology is expected to reach A10, or the 1nm node, around 2030, at which point physical transistor scaling will reach its end. Compute gains will depend entirely on packaging, interconnect, and architectural innovation, which is the biggest structural opportunity for the custom ASIC duopoly over the next decade.

Moore’s Law failing changes the capital structure

Second, the failure of Moore’s Law has changed the capital structure. In the past, from TSMC N5 to N3, transistor density increased 1.6 times while wafer costs rose only 18%, and cost per transistor fell 25%.

As N3 moves to N2, density can improve only 1.15 times, but wafer costs jump 50% because of process complexity, while cost per transistor instead rises 30%.

So, counterintuitively, advanced process nodes no longer make chips cheaper; instead, they use more expensive transistors to perform absolute compute tasks that can only be achieved at the most advanced nodes.

Cost-sensitive low-end SoCs such as smartwatches will still stick to older nodes like N16/N7, while top-tier AI accelerators with rigid compute requirements and tolerance for high premiums must use N3 or even N2.

Broadcom’s TPU v6e Trillium for Google is on the N3 node, TPU v7 Ironwood is on N3, and the next-generation TPU moves to N2.

Meta’s MTIA T-V1 for Meta is on the N5 node, and MTIA T-V2 moves up to N3.

OpenAI’s first in-house inference chip is confirmed on N3, and the second generation jumps directly to N2.

Apple’s server AI chip starts directly at N2.

Marvell’s Trainium 2 for AWS is on the N5 node, and Trainium 3 moves up to N3. MRVL’s Maia 100 for Microsoft is on the N5 node, and Maia 200 is on N3.

All next-generation flagship XPUs from hyperscalers are entering the N3-to-N2 transition window.

This window roughly covers 2026 to 2028, which happens to correspond to Broadcom’s guided AI revenue target of more than $100 billion in FY27, and also to Marvell’s implied path from about $8 billion in data center revenue in FY27 toward nearly $20 billion in FY29.

Backside power delivery and High-NA EUV

Over the next five years, the industry has two important technology paths: backside power delivery and High-NA EUV.

Among them, High-NA EUV is the next-generation lithography technology led by ASML. When AI chips shrink to about 1.4 nm equivalent, transistor density per unit area can rise by more than 1.3 times versus 2nm, corresponding to another step up in single-chip compute.

If deployment is delayed, the entire industry will be forced to shift earlier toward more aggressive packaging solutions and system-level architectural innovation to raise compute.

High-NA EUV is likely to be delayed by 12 to 18 months, because mask costs, resist materials, and metrology tools all need to be re-adapted, which is favorable for Broadcom, Marvell chip design, and TSMC.

System-level integration is replacing transistor scaling as the new engine of compute growth

In 2010, packaging costs accounted for about 5% to 8% of total chip cost; by 2020, that share had risen to 12% to 15%; and by 2026, for flagship AI accelerators, packaging costs have generally exceeded 30%, with some extreme designs approaching 40%.

The reason is that packaging has become the key bottleneck determining both chip performance ceilings and supply capacity.

First, to clarify the concept: the wafer is the raw material, the bare die is the semi-finished product, and the packaged and tested chip is the final product.

First, the mask limit, at the physical level, constrains single-die area to around 858 square millimeters, so AI chips are moving from ever-larger single dies to multi-die integration.

Second is the memory wall problem. The number of HBM stacks a single chip can support is limited by the number of HBM interfaces that can fit along the die edge. To keep increasing bandwidth, HBM must be physically brought closer to the logic die and connected directly through wide, high-speed interfaces.

Third, interconnect energy consumption has already exceeded compute energy consumption itself, making integrated packaging the only feasible engineering path.

So whoever controls advanced packaging controls the real shipment ceiling for AI accelerators. The answer is TSMC.

CoWoS is TSMC’s 2.5D packaging platform launched in 2011. Its basic structure has three layers: the bottom layer is an organic substrate, the middle layer is a silicon interposer, and the top layer consists of logic dies and HBM dies.

When CoWoS was first introduced, it mainly served high-end GPUs and FPGAs. It entered the mainstream AI accelerator market in 2016 and became standard for hyperscaler flagship XPUs starting in 2022.

Over the past several decades, the more advanced the process, the smaller the transistors, the more transistors on the chip, the stronger the performance, and the lower the power consumption. Customers were willing to keep moving to advanced nodes because this was not only a technological upgrade, but also an economic one.

But this logic begins to change from 3nm to 2nm. That is the node we are experiencing now.

That is, the failure of Moore’s Law mentioned earlier has changed the capital structure.

The first layer of the advanced process cost system is NRE, or non-recurring engineering cost, the one-time engineering development cost, including architecture definition, IP licensing, RTL design, verification, physical design, timing closure, power optimization, packaging co-design, test planning, EDA tool fees, and more.

The second layer is tape-out and masks. The more advanced the node, the more complex the masks, the more EUV layers, and the higher the cost of trial and error. Once the chip is designed, it must be handed to the foundry for pilot production, that is, tape-out. The losses from a failed tape-out are enormous, including a 6- to 9-month product window, customer deployment timing, TSMC capacity planning, HBM procurement schedules, and packaging resource allocation, among other things.

The third layer is wafer and yield cost.

In the early mass-production stage of 2nm, the cost per die may be significantly higher than 3nm.

So, 2nm is the industry watershed

For hyperscalers, the total cost of generating, processing, or understanding each token matters more.

At the same power consumption, can the chip run more inference? In the same rack, can the chip deliver higher compute density? For the same dollar spent on electricity and depreciation, can it serve more user requests? Can it reduce inference cost per million tokens? Can it improve the gross margin of AI products?

As long as the workload is stable enough and volume is large enough, custom chips can outperform general-purpose solutions on lifecycle cost.

So, the rise of custom ASIC is not because customers suddenly like in-house development; it is because advanced nodes are too expensive, general-purpose GPUs are too expensive, and AI inference and training scale are too large.

Broadcom and Marvell’s value lies in complexity management

Broadcom and Marvell provide a full set of complexity management capabilities, including an existing IP library, SerDes, PHY, interconnect, packaging co-design, TSMC process experience, yield ramp experience, mass-production test experience, and the systems understanding accumulated through long-term cooperation with hyperscalers.

In other words, the more complex the 2nm process, the more customers need external co-design partners. The higher the advanced process cost, the higher the trial-and-error cost, and the greater the value of Broadcom and Marvell.

Here, two concepts need to be introduced.

Design-Technology Co-Optimization (DTCO). Chip design participates in the collaborative definition of standard cells, SRAM, design rules, power paths, and timing models during the process development stage.

System-Technology Co-Optimization (STCO). AI chip optimization must consider logic die, HBM, CoWoS, substrate, optical interconnect, rack network, power, and cooling together.

The more complex the process, the more customers need experienced external co-design partners. These two concepts explain why AVGO and MRVL’s moats keep deepening.

Broadcom and Marvell are effectively selling complexity insurance. Customers pay not only for design, but also a premium to reduce project failure probability, shorten time to mass production, improve yield certainty, and strengthen supply-chain coordination.

Broadcom’s advantage lies in stronger system completeness, ASIC co-design capability, switching chips, SerDes, PHY, Ethernet, packaging experience, and a larger customer base.

More importantly, Broadcom also has strong cash flow from its software business, making it look more like a composite platform of AI semiconductors + infrastructure software cash flow in the capital markets.

Marvell’s advantage is that its AI data center business is more pure, and it is becoming increasingly important in optical interconnect, DSP, PAM4, data center networking, and custom silicon projects.

Marvell is not as diversified as Broadcom, and it does not have software cash flow support like VMware. But precisely because it is more pure, once major projects from AWS, Microsoft, and other large customers ramp successfully, revenue leverage will be more pronounced.

The key question going forward is,

whether the trend of AI capital expenditure shifting from general-purpose GPUs to custom ASICs will continue. If it does, Broadcom and Marvell are no longer traditional chip design service providers, but key infrastructure suppliers in hyperscaler in-house compute systems.

But if 2nm costs prove too high and customers slow their migration, Broadcom and Marvell’s revenue recognition will be delayed. If Nvidia offers semi-custom solutions, Broadcom and Marvell’s long-term margins will also be reassessed.

Nvidia has already made a strategic investment in Marvell, so Broadcom really has to go head-to-head with Nvidia.

The necessity of hyperscaler in-house ASICs

Hyperscaler in-house ASICs make sense when AI workloads are large enough, stable enough, and predictable enough to move part of the AI workload from general-purpose GPUs to custom ASICs, serving their own business at a lower unit cost rather than replacing Nvidia.

Nvidia GPUs have advantages in generality, software ecosystem, developer ecosystem, and flexibility for training frontier models. For new models, new algorithms, new frameworks, and new operators, GPUs are still the safest, fastest, and most general choice.

But once AI services enter large-scale commercialization, the cost structure changes, and inference overtakes training as the dominant workload.

Large-scale inference, recommendation, ad ranking, search, voice, translation, image generation, code completion, and similar AI workloads become highly suitable for customization once they reach massive scale and stable patterns.

Google was the earliest practitioner, the first to prove that in-house ASICs could become a long-term platform rather than a one-off project.

TPU was designed for AI workloads within its own ecosystem, from search, ads, translation, and recommendations to Gemini and Google Cloud AI, becoming one of the core components of Google AI.

Google is a typical Broadcom customer, with a clear long-term roadmap, stable chip generations, and extremely high requirements for high-end interconnect and system co-optimization.

AWS is a cloud infrastructure provider. So AWS’s Trainium and Inferentia are designed to give cloud customers cheaper, more controllable, and higher-value AI compute.

Microsoft’s demand is concentrated in Azure OpenAI, GitHub Copilot, Microsoft 365 Copilot, Bing, Windows AI, and enterprise AI services. Its in-house Maia is not only about cost reduction, but also about infrastructure choice, so AI can be migrated to more controllable internal chips, lowering long-term costs and improving supply-chain resilience.

Meta’s MTIA demand is similar, serving recommendation systems, ad ranking, content delivery, and the social graph.

A deep dive into Broadcom $AVGO

Broadcom’s business is mainly divided into four areas,

1) custom AI accelerators;

2) switching chips, Ethernet, NICs, and fabric in AI data centers;

3) high-speed I/O capabilities such as SerDes, PHY, CPO, and optical interconnect;

4) software businesses acquired through VMware.

This is the biggest difference between Broadcom and many AI semiconductor companies. Many companies only have one layer of business, either GPU, HBM, or optical modules. Broadcom is positioned across multiple key points in AI data centers at the same time.

Broadcom’s business is built through continuous acquisitions, integration, cutting non-core costs, retaining high-margin product lines, and improving cash flow conversion, forming a very distinctive capital allocation model. The underlying logic is highly consistent.

Wireless chips, broadband chips, enterprise storage, network switching, SerDes, ASIC, and VMware software all share the same characteristics: high customer switching costs, long design cycles, long lifecycles, high barriers to entry, and strong gross margins and cash flow quality.

So Broadcom is not a traditional innovation-driven semiconductor company; it is a complexity asset operations company, good at turning complex product lines into long-term cash flow assets.

Hyperscaler custom AI ASICs are also a business with extremely high complexity, extremely high switching costs, and an extremely long lifecycle. Once a customer chooses Broadcom to co-develop a generation of AI accelerators, the relationship does not end with a single chip.

And ASICs are not developed entirely from scratch for every customer. What customers need is adaptation to different AI workloads, such as Google’s TPU, Meta’s MTIA, OpenAI’s inference chip, and Apple’s private-cloud AI chip; the requirements are all different.

But Broadcom can reuse SerDes, PHY, die-to-die collaboration, packaging experience, test flows, and mass-production methods at the underlying level.

A hyperscaler-scale AI ASIC contains at least six key modules,

1) matrix compute arrays;

2) on-chip SRAM and cache systems;

3) HBM;

4) interconnect modules;

5) SerDes / PHY;

6) power management and other related modules.

SerDes must ensure signal integrity, power consumption, bit error rate, and reliability at extremely high data rates. The accumulation cycle is usually measured in years and cannot be quickly replicated by simply adding people in the short term.

Data transmission between chips, between servers, between racks, and between data centers determines the utilization rate of the entire AI data center cluster.

Broadcom has a monopoly-like position in this field.

The Tomahawk series of switching chips dominates the high-speed backbone network of AI data centers, and the Tomahawk 5 single-chip throughput reaches 51.2 Tbps, designed for ultra-high-bandwidth scenarios.

The Jericho series focuses on handling the “microbursts” common in AI training. Through hardware-level traffic control mechanisms, it eliminates buffer overflows at the circuit-logic level and achieves lossless transmission at the physical layer, rather than relying on software-protocol retransmission after the fact.

At present, in Ethernet-based AI data center networks, Broadcom’s commercial switching chips hold an absolute dominant position. The only real competition comes from Nvidia’s InfiniBand solution, but outside Nvidia itself, the industry as a whole is strongly pushing the Ethernet replacement path.

SerDes / PHY / optical interconnect: Broadcom’s underlying I/O pricing power

Switching chips determine the data scheduling capability inside AI data centers, while SerDes, PHY, and optical interconnect determine whether data can flow stably at sufficient scale across much larger clusters with low enough power consumption, high enough reliability, and enough bandwidth.

SerDes stands for serializer / deserializer. Its role is to convert parallel data inside the chip into high-speed serial signals for transmission, and then convert them back at the other end.

Because the larger the AI cluster, the more important data movement becomes. Every cross-chip, cross-board, cross-switch, and cross-rack communication passes through high-speed I/O. The higher the speed, the more signal integrity, power consumption, heat dissipation, and bit error rate become issues.

That is also why high-end SerDes is one of the hardest areas in analog and mixed-signal design. High-end SerDes requires years of product iteration, silicon validation, on-site customer debugging, packaging co-design, and system-level issue localization.

If a hyperscaler just wants to make a chip, there may be many design service providers to choose from. But if it wants to turn an AI ASIC into a system product that can interconnect, fit into racks, iterate across generations, and be jointly optimized with HBM, CoWoS, switching networks, and optical interconnect, the options narrow quickly.

This is Broadcom’s second source of pricing power: the ability to scale and reuse underlying I/O IP.

VMware: software cash flow will affect AI ASIC valuation

VMware has two important effects on Broadcom’s AI valuation,

1) it provides cash flow;

2) it provides an entry point into enterprise infrastructure.

After acquiring VMware, Broadcom added a high-margin infrastructure software business with better cash flow quality, providing a relatively stable cash flow buffer.

This turns Broadcom into a composite platform of AI semiconductor growth + infrastructure software cash flow.

That does not mean VMware has no risk. After Broadcom acquired VMware, the market has also continuously discussed customer migration, pricing pressure, and ecosystem friction. Some enterprises have tried to reduce their reliance on VMware, which shows that VMware is not a perfect risk-free cash flow asset.

But from Hock Tan’s capital allocation logic, VMware’s strategy is not to maximize the number of customers, but to pursue high-value enterprise customers, high profit margins, and a more concentrated product portfolio.

This is consistent with how Broadcom integrated CA and Symantec Enterprise: cutting low-return businesses, retaining core customers, increasing subscription penetration, and improving margins and cash flow conversion.

In an upcycle, ASIC and data center businesses provide growth leverage. In a downturn, VMware provides a cash flow buffer. That cash flow can in turn continue to support dividends, buybacks, M&A integration, and the next round of AI infrastructure investment.

A deep dive into Marvell $MRVL

Is Marvell really the most valuable second supplier of custom silicon after Broadcom, or is it a high-beta cyclical stock whose AI narrative has already been pulled forward? That is the core question in understanding Marvell.

Marvell and Broadcom are not the same kind of company

Marvell cannot simply be described as another Broadcom.

Broadcom’s strength is platformization. ASICs, AI data centers, SerDes / PHY, VMware software cash flow, and Hock Tan’s acquisition discipline together support its valuation framework.

Marvell’s story is more concentrated on AI data centers, especially ASICs, optical interconnect, DSP, Ethernet switching, PCIe retimers, AEC DSP, and scale-up, scale-out, and scale-across expansion.

So $MRVL is more like a beta AI data center infrastructure stock.

If customer projects ramp successfully, revenue leverage will be more direct than Broadcom’s; but if customer timing is delayed or optical interconnect pricing pressure intensifies, the stock will also be more sensitive.

Marvell’s positioning: from a storage/network chip company to an AI data center connectivity platform

Ten years ago, Marvell was mainly viewed by the market as a storage controller, enterprise networking, and communications infrastructure chip company.

After Matt Murphy took over, the company was repositioned from a traditional semiconductor supplier into a data infrastructure semiconductor company.

This positioning matters. Because AI data centers are not just about GPUs, and not just about ASICs.

Behind large-scale AI clusters lies an entire data infrastructure. Compute, memory, network, optical modules, switching chips, PCIe, retimers, DSP, CPO, NPO, DCI, rack interconnect, and inter-data-center interconnect are all indispensable.

The need in a data center is not just how fast the chips compute, but whether tens of thousands of GPUs or XPUs can be connected into a system with high utilization, low latency, low packet loss, and scalability. When training large models, tens of thousands of GPUs or XPUs need to continuously synchronize parameters and gradients.

When inference becomes commercialized at scale, the system must keep serving user requests under high concurrency and low latency.

Once Agentic AI workloads emerge, the problem becomes even more complex. Contexts become longer, tool calls increase, multi-turn interactions rise, and the model is no longer a one-input, one-output system; it keeps reading, calling, returning, and reasoning again.

This will further increase interconnect pressure inside data centers and between data centers.

So Marvell’s opportunity lies in standing at the key nodes of data movement. This is also why Marvell’s relationship with Nvidia is becoming an important strategic complement to the Nvidia AI ecosystem.

This is the first difference between Marvell and Broadcom. Broadcom is more like a composite platform within AI infrastructure, while Marvell is more like a connectivity platform within AI data centers.

Marvell’s AI revenue is not a single ASIC, but a portfolio of data center products

Marvell’s AI business can be broken into four layers,

1) ASICs, meaning custom AI accelerators or related compute chips designed for hyperscalers;

2) ASIC attach, meaning the connectivity, control, I/O, and support chips required around a customer’s in-house XPU.

3) Optics / DSP, meaning the digital signal processors, PAM4 DSP, coherent DSP, driver, TIA, and related components used in 800G and 1.6T optical interconnect.

4) Switching / Retimer / DCI, meaning Ethernet switch chips, PCIe retimers, active cable DSPs, data center interconnect modules, and similar products.

In Marvell’s FY2027 Q1 earnings report, the company explicitly stated that the upgraded revenue outlook was driven by multiple AI-related products: 800G and 1.6T scale-out optical solutions, 51.2T Ethernet scale-out switches, scale-up optical solutions for NPO and CPO, scale-across data center interconnect modules, and custom ASIC and ASIC attach solutions.

Three concepts need to be explained here,

1) Scale-up refers to connecting multiple accelerators within a single server, a single rack, or a relatively tight system to improve collaboration efficiency within one compute domain.

2) Scale-out refers to connecting more servers, more racks, and more nodes to form a larger AI cluster.

3) Scale-across refers to interconnects across data centers, across regions, and across clusters.

Taken together, Marvell’s main business is to participate as much as possible in the data movement chain of AI data centers, from XPU to optical interconnect, from inside the rack to between racks, from scale-up to scale-out to scale-across.

Marvell is betting that the bottleneck in AI data centers is shifting from single-chip compute capability to data movement capability. As long as this trend continues, Marvell has the chance to benefit in multiple segments at once.

But conversely, this also explains why Marvell’s valuation debate is more intense.

ASICs need to ramp, optical modules need to upgrade, DSP needs to retain value, switches need to enter more AI networks, and retimers and DCI need to follow data center expansion. If any one link falls short, market pricing will be affected.

So the question is whether Marvell can turn AI data center data-movement demand into sustained revenue growth across its product portfolio. If it can, Marvell is not just a regular networking chip company, but an AI data center connectivity platform. If it cannot, the market will reprice it as a high-beta cyclical stock whose AI narrative has been pulled forward.

Celestial AI: Marvell bought long-term option value on scale-up optical interconnect

The acquisition of Celestial AI is a case that must be discussed in detail. This deal did not buy near-term revenue; it bought a technology ticket to the next generation of AI scale-up interconnect inside systems.

Marvell completed its acquisition of Celestial AI in February 2026. Celestial AI’s core asset is its Photonic Fabric optical interconnect technology, aimed at enabling high-bandwidth, low-power, tightly integrated connections in next-generation AI and cloud data center architectures.

As the number of XPUs inside a single AI system keeps increasing, HBM keeps getting more expensive, and model parallelism and expert parallelism become more complex, high-bandwidth, low-latency interconnect within nodes and within racks will become increasingly important.

Traditional electrical interconnects will face increasing limitations in power consumption, distance, and bandwidth density. If optical interconnect can enter the system earlier, it may change the architecture of ASIC clusters.

Marvell also explicitly stated that Celestial AI’s technology and team will be integrated into Marvell’s data center business to strengthen end-to-end connectivity for next-generation AI systems.

Marvell disclosed that Celestial AI’s initial revenue contribution is expected to begin in the second half of FY2028 and reach an annualized rate of $500 million in FY2028 Q4. By FY2029 Q4, annualized revenue is expected to double to $1 billion. At the same time, the acquisition is expected to add about $50 million in annual non-GAAP operating expenses.

Nvidia’s investment in Marvell brings ASICs within the boundary

Nvidia certainly does not want hyperscaler in-house ASICs to completely bypass its systems ecosystem. If customers insist on developing their own chips, the better choice is to allow those in-house ASICs to connect to Nvidia’s ecosystem such as NVLink.

As AI inference scales, internal AI workloads stabilize, and data center cost pressure rises, customers will certainly keep advancing in-house ASICs.

So Nvidia introduced NVLink Fusion, allowing third parties to enter Nvidia’s internet ecosystem to some extent. Even if customers use ASICs provided by Marvell, they may still use Nvidia’s interconnect technology.

Marvell’s ideal position is not merely to become a subsidiary supplier to Nvidia, but to become a connectivity-layer supplier needed by multiple AI system paths.

So in the past, the market viewed MRVL mostly by comparing it with Broadcom, asking whether Marvell could become the second-largest ASIC supplier after Broadcom.

Now there is an additional valuation logic: can Marvell stand between the Nvidia ecosystem and the hyperscaler in-house ecosystem at the same time, becoming a connectivity platform needed by both sides?

If so, its valuation potential will be greater than that of a pure ASIC design company, because it controls system connectivity.

Summary comparison between Broadcom and Marvell

Broadcom is ASIC, Marvell is optical interconnect. That is a rough conclusion. It is not wrong, but it is too simplistic.

Broadcom’s stronger position is in the scale-up / scale-out Ethernet network structure, as well as switching chips, SerDes / PHY, network cards, and networking platforms.

Its core capability is to connect a large number of compute nodes in AI data centers into a scalable, schedulable, mass-producible system through high-performance networks. Tomahawk, Jericho, SerDes, PHY, NICs, CPO, and ASIC together form Broadcom’s system-level control points in AI data centers.

So AVGO’s position is more oriented toward the control point of the network switching matrix.

Anyone building a large-scale AI cluster needs high-performance switching chips, low-power high-speed I/O, congestion control, Ethernet architecture, and system-level tuning capabilities. That is Broadcom’s advantage.

Marvell’s stronger position is in DSP, PAM4, coherent optical communications, ASIC peripheral capabilities, data center interconnects, silicon photonics, and semi-custom scale-up interconnect after entering NVLink Fusion.

Its core capability is not to control the entire network structure like Broadcom, but to capture as many key connection points as possible in the AI data movement chain.

So Marvell’s position is more oriented toward multiple attachment points in the data exchange chain.

Marvell is not the absolute leader in every layer, but it participates in many segments, including ASIC peripherals, inside optical modules, data center interconnects, PCIe retimers, active cable DSPs, silicon photonic interconnects, and scale-up interconnect. Its revenue comes more from the continuously increasing demand for connection chips as AI data flows.

And hyperscalers’ procurement philosophy is usually: buy the best solution in the short term, support the second supplier in the medium term, and promote open standards in the long term, while splitting the supply chain across different workloads. That is one important reason why MRVL’s stock can have stronger explosive upside.