Broadcom and Marvell are Dominating the Core Narrative of AI Data Centers

Broadcom and Marvell are the two dominant companies in custom ASIC.

Custom ASIC is one of the fastest-growing segments in semiconductors. The reason this matters, or the main point I want to make here, is

Moore’s Law has gradually weakened after the 28nm process node, meaning shrinking chip area no longer brings higher transistor density, greater computing power, lower power consumption, or faster computation through higher 0/1 switching frequencies.

At today's 3 nm and 2 nm nodes, the design and tape-out cost for a single wafer exceeds $500 million, and the industry's entire economic structure will certainly have to be reorganized.

How will it be reorganized?

If you are Google, and you spend more than $50 billion each year on power and depreciation costs related to TPU training and inference, then a custom chip that can cut token inference cost by 30% means substantial savings.

Over the past five years, an increasing share of Hyperscaler's capital expenditures has flowed into self-developed chips, while the marginal dollar increase of Nvidia GPUs available on the market has gradually plateaued. Google TPU v7, AWS Trainium 2 and Trainium 3, Microsoft Maia 100 and Maia 200, Meta MTIA, and Apple’s in-house AI server chip are officially confirmed in 2026.

Globally, there are really only two companies capable of handling ASIC co-design work at hyperscaler scale: Broadcom and Marvell. According to industry research by Tom's Hardware, these two companies together account for about 95% of the hyperscaler custom AI accelerator co-design market.

What this 95% concentration means is: over the next five to ten years, among all the AI capital expenditures hyperscalers deploy, the creation of every internal XPU will almost always go through one of these two companies.

The rise of custom ASIC is not a business story; it is an economic restructuring forced into existence after physics reached its limit

High customer concentration

First, custom ASIC customers are highly concentrated among the leading hyperscalers.

In 1974, Dennard proposed a scaling law at IBM Research, finding that when chips were shrunk, performance could increase while power consumption remained constant.

But by the 90nm node, severe leakage issues imposed by physical constants had prevented voltage from continuing to fall proportionally, causing power density to surge. This was the physical reason CPU clock speeds stopped increasing around 2005, and the starting point for the later rise of multi-core architectures.

Starting from 28nm, cost per transistor no longer fell; instead, it began to rise, driving manufacturing and design costs sharply higher.

Today, 3nm tape-out costs as much as $500 million, and 2nm is closer to $1 billion. Such extremely high fixed costs mean that only the leading data center giants, consuming millions of chips each year, can amortize the cost through massive output.

According to TSMC and industry roadmaps, process technology is expected to reach A10, or the 1nm node, around 2030, at which point physical transistor scaling will come to an end. Compute gains will depend entirely on packaging, interconnect, and architectural innovation, which is the biggest structural opportunity for the custom ASIC duopoly in the next decade.

Moore’s Law Weakening Changes the Capital Structure

Second, the failure of Moore’s Law has changed the capital structure. Previously, from TSMC N5 to N3, transistor density increased 1.6 times while wafer cost rose only 18%, and cost per transistor fell 25%.

When N3 moves to N2, density can only improve 1.15 times, but wafer cost rises 50% because of process complexity, while cost per transistor increases 30%.

So, counterintuitively, advanced process nodes no longer make chips cheaper; instead, they use more expensive transistors to perform the absolute compute tasks that can only be achieved at the most advanced nodes.

Low-end cost-sensitive SoCs like smartwatches will remain on older nodes such as N16/N7, while leading AI accelerators with hard compute requirements and willingness to pay a high premium must use N3 or even N2.

Broadcom’s TPU v6e Trillium for Google is on the N3 node, TPU v7 Ironwood is on N3, and the next-generation TPU moves to N2.

Meta’s MTIA T-V1 for Meta is on the N5 node, and MTIA T-V2 moves up to N3.

OpenAI’s first in-house inference chip is confirmed on N3, and the second generation jumps straight to N2.

Apple’s AI server chip starts directly at N2.

Marvell’s Trainium 2 for AWS is on the N5 node, and Trainium 3 moves up to N3. MRVL’s Maia 100 for Microsoft is on the N5 node, and Maia 200 is on N3.

All next-generation flagship XPUs from hyperscalers are entering the N3-to-N2 transition window.

This window roughly covers the period from 2026 to 2028, aligning with Broadcom’s guided AI revenue target of more than $100 billion in FY27, and also with Marvell’s implied roadmap from about $8 billion in data center revenue in FY27 to nearly $20 billion in FY29.

Backside power delivery and High-NA EUV

Over the next five years, the industry has two important technology directions: backside power delivery and High-NA EUV.

Among them, High-NA EUV is the next-generation lithography technology led by ASML. When AI chips shrink to roughly the equivalent of 1.4 nm, transistor density per unit area could increase by more than 1.3 times versus 2nm, corresponding to another step up in compute per chip.

If deployment is delayed, the entire industry will be forced to move earlier toward more aggressive packaging solutions and system-level architectural innovation to raise compute.

High-NA EUV is likely to be delayed by 12 to 18 months, because the costs of masks, resist materials, and metrology tools all need to be adapted again, which benefits Broadcom, Marvell’s chip designs, and TSMC.

System-level integration is replacing transistor scaling as the new engine of compute growth

In 2010, packaging costs accounted for about 5% to 8% of total chip costs; by 2020, that figure had risen to 12% to 15%; and by 2026, for flagship AI accelerators, packaging costs had generally exceeded 30%, with some extreme designs approaching 40%.

The reason is that packaging has become the key bottleneck determining both chip performance limits and supply capacity.

First, to clarify the concept: wafer is the raw material, bare die is the semi-finished product, while packaged and tested chip is the final product.

First, the mask limit, at the physical level, constrains single-die area to about 858 millimeters vuông, so AI chips are shifting from increasingly large single die to multi-die integration.

Second is the memory wall issue. The number of HBM stack that a single chip can support is limited by the number of HBM interfaces that can fit along the edge of the die. To continue increasing bandwidth, HBM must be physically brought closer to the logic die and connected directly through wide, high-speed interfaces.

Third, the power consumption of interconnect has surpassed compute power, making integrated packaging the only technically feasible path.

Therefore, whoever controls advanced packaging controls the actual delivery ceiling for AI accelerators. The answer is TSMC.

CoWoS is TSMC's 2.5D packaging platform launched in 2011. Its basic structure has three layers: the bottom layer is the organic substrate, the middle layer is the silicon interposer, and the top layer consists of logic dies and HBM dies.

When CoWoS was first introduced, it mainly served high-end GPUs and FPGAs. It entered the mass-market AI accelerator market in 2016 and has become the standard for hyperscaler flagship XPU since 2022.

Over the past few decades, the more advanced the process, the smaller the transistor, the more transistors on the chip, the stronger the performance, and the lower the power consumption. Customers have been willing to keep moving to advanced nodes because this is not only a technological upgrade, but also an economic upgrade.

But this logic began to change from 3nm to 2nm. That is the node we are going through now.

That is, the failure of Moore’s Law mentioned earlier has changed the capital structure.

The first layer of the advanced process cost system is NRE, or non-recurring engineering cost, that is, one-time technical development cost, including architecture definition, IP licensing, RTL design, verification, physical design, timing closure, power optimization, packaging co-design, test planning, EDA tool fees, and more.

The second layer is tape-out and masks. The more advanced the node, the more complex the masks, the more EUV layers, and the higher the trial-and-error cost. Once the chip has been designed, it must be handed over to the foundry for trial production, namely tape-out. The damage from a failed tape-out is enormous, including a 6 to 9 month product window, the customer's deployment timing, TSMC's capacity plan, HBM procurement schedule, and packaging resource allocation, among many other factors.

The third layer is wafer cost and yield.

In the initial mass-production phase of 2nm, cost per die can be significantly higher than 3nm.

Therefore, 2nm is the industry's turning point

For hyperscalers, the total cost of generating, processing, or understanding each token matters more.

At the same power consumption, can the chip run more inference? In the same rack, can the chip deliver higher compute density? With the same amount spent on power and depreciation, can it serve more user requests? Can it reduce inference cost per million tokens? Can it improve the gross margin of AI products?

As long as the workload is stable enough and the scale is large enough, custom chips can outperform general-purpose solutions in lifecycle cost.

Therefore, the rise of custom ASIC is not because customers suddenly prefer to build in-house; it is because advanced nodes are too expensive, general-purpose GPUs are too expensive, and the scale of AI inference and training is too large.

The value of Broadcom and Marvell lies in complexity management

Broadcom and Marvell provide a complete set of complexity-management capabilities, including off-the-shelf IP libraries, SerDes, PHY, interconnect, packaging co-design, TSMC process experience, yield ramp experience, mass-production test experience, and the system understanding accumulated through long-term collaboration with hyperscalers.

In other words, the more complex the 2nm process becomes, the more customers need external co-design partners. The higher the advanced process cost, the greater the trial-and-error cost, and the greater the value of Broadcom and Marvell.

Here, two concepts need to be introduced.

Design-Technology Co-Optimization (DTCO). Chip design participates in the synchronous definition of standard cells, SRAM, design rules, power paths and timing models during process development.

System-Technology Co-Optimization (STCO). AI chip optimization must consider logic die, HBM, CoWoS, substrate, optical interconnect, rack network, power supply and cooling at the same time.

The more complex the process, the more customers need experienced external co-design partners. These two concepts explain why the moat of AVGO and MRVL is becoming deeper and deeper.

Broadcom and Marvell are essentially selling insurance against complexity. Customers are not only paying for design, but also paying an extra premium to reduce the probability of project failure, shorten time to mass production, improve yield certainty, and strengthen supply chain coordination.

Broadcom's advantage lies in stronger system completeness, ASIC co-design capability, switching chips, SerDes, PHY, Ethernet, packaging experience, and a larger customer base.

More importantly, Broadcom also has strong cash flow from the software segment, making the company look like a hybrid platform of AI semiconductors + infrastructure software cash flow in the capital market.

Marvell's advantage is that its AI data center business is purer, and it is becoming increasingly important in optical interconnect, DSP, PAM4, data center networking, and custom silicon projects.

Marvell is not as diversified as Broadcom, and it also does not have the cash flow support from software like VMware. But precisely because it is purer, once large projects from AWS, Microsoft, and other major customers ramp successfully, the revenue leverage will be more pronounced.

The key question in the near term is,

whether the trend of AI capital spending shifting from general-purpose GPUs to custom ASICs will continue. If so, Broadcom and Marvell are no longer traditional chip design service providers, but core infrastructure providers in hyperscaler self-built computing systems.

But if 2nm costs are too high and customers slow the transition, Broadcom and Marvell's revenue recognition will be delayed. If Nvidia provides semi-custom solutions, the long-term margins of Broadcom and Marvell will also have to be reassessed.

Nvidia has made a strategic investment in Marvell, so Broadcom really has to face Nvidia head-on.

The necessity of hyperscaler self-built ASICs

Hyperscaler self-built ASICs make sense when AI workloads are large enough, stable enough, and predictable enough to shift part of AI workload from general-purpose GPUs to custom ASICs, serving their own business operations at lower unit cost rather than replacing Nvidia.

Nvidia's GPUs have advantages in versatility, software ecosystem, developer ecosystem, and flexibility for training frontier models. With new models, new algorithms, new frameworks, and new operators, GPUs are still the safest, fastest, and most general choice.

But once AI services enter large-scale commercialization, the cost structure will change, and inference will overtake training to become the dominant workload.

Large-scale inference, recommendation, ad ranking, search, voice, translation, image generation, code completion, and similar AI workloads become very suitable for customization when they reach enormous scale and a stable pattern.

Google is the earliest practitioner, the first to prove that self-built ASICs can become a long-term platform rather than a one-off project.

TPU is designed for AI workloads within its own ecosystem, from search, ads, translation, and recommendations to Gemini and Google Cloud AI, becoming one of the core components of Google AI.

Google is a typical Broadcom customer, with a clear long-term roadmap, stable chip generations, and extremely high requirements for high-end interconnect and system co-optimization.

AWS is a cloud infrastructure provider. Therefore AWS's Trainium and Inferentia are designed to give cloud customers cheaper, more controllable, and higher-value AI computing capabilities.

Microsoft's demand is concentrated in Azure OpenAI, GitHub Copilot, Microsoft 365 Copilot, Bing, Windows AI, and enterprise AI services. Its self-built Maia is not only aimed at reducing costs, but also serves as an infrastructure choice, so AI can be shifted to more controllable internal chips, reducing long-term costs and improving supply chain resilience.

Meta's MTIA demand is similar, serving recommendation systems, ad ranking, content distribution, and the social graph.

Going deeper into Broadcom $AVGO

Broadcom's business is mainly divided into four segments,

1) custom AI accelerators;

2) switching chips, Ethernet, NIC, and fabric in AI data centers;

3) high-speed I/O capabilities such as SerDes, PHY, CPO, and optical interconnect;

4) software businesses acquired through VMware.

This is the biggest difference between Broadcom and many other AI semiconductor companies. Many companies only have one business layer, either GPU, or HBM, or optical modules. Broadcom is positioned at multiple key points in AI data centers at the same time.

Broadcom's business has been built through continuous acquisitions, integration, cutting non-core costs, retaining high-margin product lines, and improving cash conversion, forming a very distinctive capital allocation model. Its underlying logic is highly consistent.

Wireless chips, broadband chips, enterprise storage, network switching, SerDes, ASICs, and VMware software all share the same characteristics: high customer switching costs, long design cycles, long life cycles, high entry barriers, and strong gross margins and cash flow quality.

Therefore Broadcom is not a traditional semiconductor company in the innovation sense; it is a complex asset operation company, good at turning complex product lines into long-term cash-flow assets.

Hyperscaler custom AI ASICs are also a business with extremely high complexity, extremely high switching costs, and extremely long life cycles. Once a customer chooses Broadcom to co-develop a generation of AI accelerators, that relationship does not end with just one chip.

And ASICs are not developed completely from scratch for each customer. What customers need is adjustment for different AI workloads, such as Google TPU, Meta's MTIA, OpenAI's inference chips, and Apple's private-cloud AI chips; the requirements are all different.

But Broadcom can reuse SerDes, PHY, die-to-die coordination, packaging experience, test flows, and mass-production methods at the foundational layer.

A hyperscaler-scale AI ASIC contains at least six key modules,

1) computing matrix;

2) on-chip SRAM and cache systems;

3) HBM;

4) interconnect modules;

5) SerDes / PHY;

6) power management and other related modules.

SerDes must ensure signal integrity, power consumption, bit error rate, and reliability at extremely high data rates. The accumulation cycle is usually measured in years and cannot be quickly replicated simply by adding headcount in the short term.

Data transmission between chips, between servers, between racks, and between data centers determines the utilization rate of the entire AI data center cluster.

Broadcom has an almost monopolistic position in this field.

The Tomahawk switching chip family dominates the high-speed backbone networks of AI data centers, and the throughput of a single Tomahawk 5 chip reaches 51.2 Tbps, designed for ultra-high-bandwidth scenarios.

The Jericho family focuses on handling the “microbursts” commonly seen in AI training. Through hardware-level traffic control mechanisms, it eliminates buffer overflow at the circuit logic level and achieves lossless transmission at the physical layer, rather than relying on retransmission at the software protocol layer afterward.

Currently, in Ethernet-based AI data center networks, Broadcom’s commercial switching chips hold an absolute dominant position. The only real competitor is Nvidia’s InfiniBand solution, but outside Nvidia itself, the entire industry is strongly pushing the Ethernet alternative path.

SerDes / PHY / optical interconnect: Broadcom’s foundational I/O pricing power

Switch chips determine the ability to coordinate data inside AI data centers, while SerDes, PHY, and optical interconnect determine whether data can flow stably at a much larger scale between large clusters with low enough power consumption, high enough reliability, and sufficient bandwidth.

SerDes is short for serializer / deserializer. Its role is to convert parallel data inside the chip into high-speed serial signals for transmission, then convert them back at the other end.

Because the larger the AI cluster, the more important data movement becomes. Every cross-chip, cross-board, cross-switch, and cross-rack communication goes through high-speed I/O. The higher the speed, the more signal integrity, power consumption, heat dissipation, and bit error rates become issues.

That is also why premium SerDes is one of the hardest areas in analog and mixed-signal design. High-end SerDes requires years of product iteration, silicon validation, on-site debugging with customers, packaging co-design, and system-level issue isolation.

If a hyperscaler only wants to make a single chip, there may be many design service providers to choose from. But if it wants to turn an AI ASIC into a system product that can be interconnected, racked, iterated across generations, and jointly optimized with HBM, CoWoS, switching networks, and optical interconnect, the choices quickly narrow.

This is the second source of Broadcom’s pricing power: the ability to scale and reuse foundational I/O IP.

VMware: software cash flow will affect AI ASIC valuation

VMware has two important effects on Broadcom’s AI valuation,

1) it generates cash flow;

2) it provides an entry point into enterprise infrastructure.

After acquiring VMware, Broadcom added a high-margin infrastructure software segment with better cash flow quality, creating a relatively stable cash flow buffer.

This turns Broadcom into a composite platform of AI semiconductor growth + infrastructure software cash flow.

That does not mean VMware has no risks. After Broadcom acquired VMware, the market has also continuously discussed customer migration, pricing pressure, and ecosystem friction. Some enterprises have tried to reduce their dependence on VMware, which shows that VMware is not a perfect cash-flow asset without risk.

But from Hock Tan’s capital allocation logic, VMware’s strategy is not to maximize the number of customers, but to pursue high-value, high-margin enterprise customers and a more concentrated product portfolio.

This is consistent with how Broadcom integrated CA and Symantec Enterprise: cut low-yield businesses, retain core customers, increase subscription penetration, and improve margins and cash conversion.

In growth cycles, ASIC and the data center segment create growth leverage. In downturn cycles, VMware provides a cash flow buffer. That cash flow in turn continues to support dividends, share buybacks, M&A integration, and the next round of investment in AI infrastructure.

Deep dive on Marvell $MRVL

Is Marvell really the second most valuable custom silicon supplier after Broadcom, or just a high-beta cyclical stock whose AI story has been pulled forward? That is the core question for understanding Marvell.

Marvell and Broadcom are not the same kind of company

Marvell cannot simply be described as another Broadcom.

Broadcom’s strength lies in platformization. ASICs, AI data centers, SerDes / PHY, VMware software cash flow, and Hock Tan’s M&A discipline together support the company’s valuation framework.

Marvell’s story is more concentrated on AI data centers, especially ASICs, optical interconnect, DSP, Ethernet switching, PCIe retimers, AEC DSP, and the expansion of scale-up, scale-out, and scale-across.

So $MRVL looks more like a higher-beta AI data center infrastructure stock.

If customer projects accelerate successfully, the revenue leverage will be more direct than Broadcom’s; but if customer timing is delayed or optical interconnect pricing pressure intensifies, the stock will also be more sensitive.

Marvell’s positioning: from a storage/network chip company to an AI data center connectivity platform

Ten years ago, Marvell was mainly seen by the market as a storage controller, enterprise networking, and communications infrastructure chip company.

After Matt Murphy took over, the company was repositioned from a traditional semiconductor supplier to a data infrastructure semiconductor company.

This positioning matters a great deal. Because AI data centers are not just about GPUs, and they are not just about ASICs either.

Behind large-scale AI clusters lies an entire data infrastructure. Compute, memory, networks, optical modules, switch chips, PCIe, retimers, DSPs, CPO, NPO, DCI, rack links, and inter-data-center links are all indispensable components.

The demand of a data center is not just about how fast the compute chips are, but whether tens of thousands of GPUs or XPUs can be connected into a system with high utilization, low latency, low packet loss, and scalability. When training large models, tens of thousands of GPUs or XPUs need to continuously synchronize parameters and gradients.

When inference is commercialized at scale, the system must continue serving user requests with high concurrency and low latency.

When Agentic AI workloads emerge, the problem becomes even more complex. Contexts become longer, tool calls increase, multi-turn interactions increase, and the model is no longer a one-input, one-output system; it keeps reading, calling, returning, and reasoning again.

This will continue to increase the pressure on interconnects within data centers and between data centers.

Therefore, Marvell's opportunity lies in sitting at the key nodes of data movement. This is also why Marvell's relationship with Nvidia is becoming an important strategic complement to Nvidia's AI ecosystem.

This is the first difference between Marvell and Broadcom. Broadcom is more like a consolidated platform in AI infrastructure, while Marvell is more like a connectivity platform in AI data centers.

Marvell's AI revenue is not a single ASIC, but a data center product portfolio

Marvell's AI business can be divided into four layers,

1) ASICs, meaning custom AI accelerators or related compute chips designed for hyperscalers;

2) ASIC attach, meaning the connectivity, control, I/O, and support chips needed around the customer's self-developed XPU.

3) Optics / DSP, meaning digital signal processors, PAM4 DSP, coherent DSP, driver, TIA, and related components used in 800G and 1.6T optical interconnects.

4) Switching / Retimer / DCI, meaning Ethernet switch chips, PCIe retimers, DSPs for active cables, data center interconnect modules, and similar products.

In Marvell's FY2027 Q1 earnings report, the company clearly stated that the upgraded revenue outlook was driven by many AI-related products: 800G and 1.6T scale-out optical solutions, 51.2T scale-out Ethernet switches, NPO and CPO scale-up optical solutions, scale-across data center interconnect modules, and custom ASIC and ASIC attach solutions.

Three concepts need to be explained here,

1) Scale-up refers to connecting multiple accelerators within a single server, a single rack, or a relatively tightly coupled system to improve coordination efficiency within a compute domain.

2) Scale-out refers to connecting more servers, more racks, and more nodes to form a larger AI cluster.

3) Scale-across refers to links between data centers, between regions, and between clusters.

Taken together, Marvell's core business is to participate as much as possible in the data movement chain of AI data centers, from XPU to optical interconnect, from inside the rack to between racks, from scale-up to scale-out to scale-across.

Marvell is betting that the bottleneck in AI data centers is shifting from the compute capability of a single chip to data movement capability. As long as this trend continues, Marvell has the opportunity to benefit in multiple segments at once.

But on the flip side, this also explains why the debate over Marvell's valuation is more intense.

ASICs need to accelerate, optical modules need to upgrade, DSP needs to preserve value, switches need to penetrate more AI networks, and retimers and DCI need to keep pace with data center expansion. If any link falls short of expectations, market valuation will be affected.

So the question is whether Marvell can turn AI data center data movement demand into sustainable revenue growth across its entire product portfolio. If it can, Marvell is not just an ordinary networking chip company, but an AI data center connectivity platform. If not, the market will re-rate it as a high-beta cyclical stock with an AI story that has been pulled forward.

Celestial AI: Marvell has bought a long-term value option on scale-up optical interconnects

The acquisition of Celestial AI is a case that needs detailed discussion. The deal did not buy short-term revenue; it bought a technology ticket for the next generation of scale-up AI interconnects inside the system.

Marvell completed the acquisition of Celestial AI in February 2026. Celestial AI's core asset is the Photonic Fabric optical interconnect technology, aimed at enabling high-bandwidth, low-power, tightly integrated connections in next-generation AI and cloud data center architectures.

As the number of XPUs in a single AI system continues to increase, HBM continues to become more expensive, and parallel and expert parallel models become more complex, high-bandwidth, low-latency interconnects within the node and within the rack will become increasingly important.

Traditional electrical interconnects will face growing limitations in power consumption, distance, and bandwidth density. If optical interconnect can enter the system earlier, it can change the architecture of ASIC clusters.

Marvell has also stated clearly that Celestial AI's technology and team will be integrated into Marvell's data center business to strengthen end-to-end connectivity for next-generation AI systems.

Marvell disclosed that Celestial AI's initial revenue contribution is expected to begin in the second half of FY2028 and reach an annualized rate of $500 million in FY2028 Q4. By FY2029 Q4, annualized revenue is expected to double to $1 billion. At the same time, this acquisition is expected to increase annual non-GAAP operating expenses by about $50 million.

Nvidia's investment in Marvell brings ASICs inside the boundary

Certainly Nvidia does not want hyperscalers’ internal ASICs to completely bypass its own systems ecosystem. If customers are determined to develop their own chips, a better option is to allow those internal ASICs to connect to Nvidia’s ecosystem through something like NVLink.

As AI inference scales, internal AI workloads become more stable, and as data center cost pressure rises, customers will undoubtedly continue to push for internal ASICs.

So Nvidia introduced NVLink Fusion, allowing third parties to participate to some extent in Nvidia’s internet ecosystem. Even if customers use ASICs provided by Marvell, they can still use Nvidia’s interconnect technology.

Marvell’s ideal position is not merely to be a downstream supplier to Nvidia, but to become the required connectivity-layer provider for multiple different AI system paths.

So in the past, the market mainly viewed MRVL by comparing it with Broadcom, asking whether Marvell could become the second-largest ASIC supplier after Broadcom.

Now there is an additional valuation logic: can Marvell stand at the same time between the Nvidia ecosystem and the hyperscaler internal ecosystem, becoming a connectivity platform needed by both sides?

If so, its valuation potential would be greater than that of a pure ASIC design company, because it controls system connectivity.

Brief comparison between Broadcom and Marvell

Broadcom is ASIC, Marvell is optical interconnect. That is a preliminary conclusion. It is not wrong, but it is too simple.

Broadcom’s stronger position lies in its Ethernet scale-up / scale-out network architecture, as well as switching chips, SerDes / PHY, network interface cards, and networking platforms.

Its core capability is connecting a large number of computing nodes in AI data centers into a scalable, schedulable, and mass-producible system through high-performance networks. Tomahawk, Jericho, SerDes, PHY, NICs, CPO and ASIC together form Broadcom’s system-level control points in AI data centers.

So AVGO’s position is more tilted toward the control points of the network switching matrix.

Anyone building a large-scale AI cluster needs high-performance switching chips, low-power high-speed I/O, congestion control, Ethernet architecture, and system-level tuning capabilities. That is Broadcom’s advantage.

Marvell’s stronger position lies in DSP, PAM4, coherent optical communications, ASIC peripheral capability, inter-data-center interconnects, silicon photonics, and semi-custom scale-up interconnect after joining NVLink Fusion.

Its core capability is not controlling the entire network architecture like Broadcom, but capturing as many key connection points as possible in the AI data movement chain.

So Marvell’s position is more tilted toward multiple binding points in the data exchange chain.

Marvell is not the absolute leader in every layer, but it participates in many segments, including ASIC peripheral, inside optical modules, inter-data-center interconnects, PCIe retimers, active cable DSPs, silicon photonic interconnect, and scale-up interconnect. Its revenue comes more from the continuously rising demand for connectivity chips as AI data moves.

And hyperscalers’ procurement philosophy is often: buy the best solution in the short term, support a second supplier in the medium term, and push open standards in the long term, while also separating the supply chain by different workloads. That is one of the important reasons why MRVL stock may have greater room for a strong breakout.